Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced that Taiwan Semiconductor Manufacturing Company (TSMC) Reference Flow 7.0 includes the use of Apache's:
-- RedHawk-LP MTCMOS dynamic verification with advanced power switches
-- RedHawk-EV modified SDF (MSDF) for full-chip STA timing
-- PsiWinder critical path timing and clock skew and jitter analyses
"Apache continues to deliver key technologies required to address design challenges at 65nm," said Ed Wan, senior director of design service marketing at TSMC. "In Reference Flow 7.0, RedHawk's support of low-power design management has been expanded to include 2-pin MTCMOS (Multiple Threshold CMOS) switches, clock-gating, and multiple voltage domains."
To identify potential low power and leakage control design issues, RedHawk-LP (Low-Power) supports mixed-mode analysis where designers can analyze how simultaneous "ON," "OFF," and "power-up" states impact the chip's sleep-to-active timing, dynamic rush current and power-line voltage drop. In addition, the FAO optimization technology enables designers to automatically remove ineffective decaps, thus reducing excessive leakage caused by devices that do not contribute to the overall power integrity of the chip.
"In addition to low power support, we've included RedHawk's MSDF chip-level timing, and PsiWinder's accurate clock skew, jitter, and critical path timing capabilities," added TSMC's Wan.
As designs move toward 65nm and below, controlling design margin for OCV (On-Chip Variation) and effects of PVT (Process Voltage Temperature) become increasingly difficult. Traditional methods of over-design and guard-banding are limiting designers' ability to achieve timing convergence with aggressive tapeout schedule. RedHawk's power-noise timing flow with MSDF allows designers to separate the true violations from the false alarms, thus providing better margin management.
"TSMC's leading process technologies have been driving the industry's most advanced flow requirements and we are pleased to see continued use of RedHawk, as well as the inclusion of PsiWinder as key components of the TSMC Reference Flow," said Andrew Yang, CEO of Apache. "The on-going collaboration between Apache and TSMC benefits our mutual customers and allows us to address their power integrity and noise management issues and increase yields."
About Apache Design Solutions
Apache is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design--such as power, signal, package / system IO, substrate, and temperature--Apache's silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor-neutral platform enables designers to adopt any industry-standard physical design flow and is certified by TSMC's 5.0 and 6.0 Reference Flow (NYSE:TSM).
Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies. For more information, visit www.apache-da.com.
Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.