Calypto(TM) Design Systems, Inc. will demonstrate its SLEC(TM) product family in Booth #628 during the 43rd Design Automation Conference (DAC) July 24-27 at San Francisco's Moscone Center.
Calypto will host a daily technical session entitled, "Sequential Equivalence Checking -- A Comprehensive Methodology from System Level Algorithms to Register Transfer Level (RTL) Implementation." Sessions will be limited to 20 people and will be held at the following times:
-- Monday: Noon and 5 p.m
-- Tuesday: Noon and 5 p.m
-- Wednesday: 9 a.m. and 5 p.m.
-- Thursday: 9 a.m.
A continental breakfast will be provided during morning sessions, lunch for noon sessions and appetizers at the 5:00 p.m. sessions.
Venkat Krishnaswamy, Calypto's vice president of Applications Engineering, will present how SLEC enables a comprehensive methodology to link System Level models to design implementation, dramatically improving productivity and verification quality in the design of multi-million gate system-on-chip (SoC) devices. Many of these devices are meant for consumer markets, which require tight schedule development, reduced power and increased performance targets. These factors -- complexity, power, performance and productivity -- are driving design teams toward higher levels of design abstraction.
Calypto recently announced availability of SLEC version 2.0, a sequential logic equivalence checking solution that enables designers to leverage their System Level model throughout their design flow. SLEC 2.0 increases capacity by 100x for System Level designs over previous releases, dramatically improves runtime and further simplifies the design debug process with counter example enhancements. These added features provide capabilities required for the broad electronic system level (ESL) market.
To register for a technical session or to schedule a SLEC demonstration, visit: www.calypto.com or R.S.V.P. to firstname.lastname@example.org.
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge system and RTL for semiconductor design, thereby saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, the Open SystemC Initiative (OSCI), Synopsys SystemVerilog Catalyst Program, and the Mentor Graphics OpenDoor program. Corporate Headquarters are located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Facsimile: (408) 850-2301. Email: email@example.com. More information about the company may be found at www.calypto.com.
Calypto and SLEC are trademarks of Calypto Design Systems, Inc. Calypto acknowledges trademarks or registered trademarks of other organizations for their respective products and services.